Texas Instruments unveiled details of a 45 nm semiconductor manufacturing process that leverages a "wet" lithography process to double the number of chips produced on each silicon wafer, increasing performance by 30 percent while reducing power consumption 40 percent.

publicité

TI's 45-nm process will be manufactured on 300-mm wafers in the DMOS6 facility in Dallas, Texas. The low-power ASIC design library will be available by the end of this year, with samples of the first SoC product delivered in 2007 and initial production in mid-2008.